Xilinx Spartan 3E on linux – frequency generator example

Xilinx developed Vivado design suite for its 7 series FPGA, for older models you still need to use ISE. I’m using ISE 14.7 webpack edition, which is free and Ubuntu 15.10. The board is the Spartan-3E FPGA Starter Kit Board with a Xilinx XC3S500E FPGA and a bunch of peripherals (it’s the model with the LCD, not the 7 segment leds).


This small post is about set up things and run s3esk_frequency_generator example.

Install cable drivers

This steps are necessary to run impact and to download the bitstream to the board (from this ubuntu thread).

sudo apt-get install fxload libusb-dev

cd /etc/udev/rules.d/
sudo cp /opt/Xilinx/14.7 /etc/udev/rules.d/50-xusbdfwu.rules
sudo cp /share/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusbdfwu.rules /etc/udev/rules.d/50-xusbdfwu.rules
sudo sed -i -e 's/TEMPNODE/tempnode/' -e 's/SYSFS/ATTRS/g' -e 's/BUS/SUBSYSTEMS/' /etc/udev/rules.d/50-xusbdfwu.rules
sudo cp /share/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb*.hex /usr/share/
sudo chmod 644 /usr/share/xusb*.hex
sudo restart udev
sudo service udev restart

Running an example design

I want to try the s3esk_frequency_generator example in order to play with the DCM. Like most of the examples it uses a PicoBlaze soft processor, this is a little bit annoying because it complicates the initial setup, but it’s good to know it and to use it.

First you need to download KCPSM3 from Xilinx website. From that folder you need to copy kcpsm3.vhd to the project folder and add it to the project.

fg_ctrl.vhd contains the following primitive v2_bscan: BSCAN_VIRTEX2 which must be changed to v2_bscan: BSCAN_SPARTAN3

Next you need a working directory with the following files:

├── pico
│   ├── fg_ctrl.psm           <- assembly source file
│   ├── KCPSM3.EXE            <- assembler
│   ├── ROM_form.coe          <- ROM configuration file
│   └── ROM_form.vhd          <- VHDL ROM file template

In the Xilinx’s examples the ROM_form.vhd is not the default one, but it is the one with JTAG_loader functionality (check the KCPSM3 folder and the docs, JTAG loader is useful during development). You need to copy JTAG_Loader_ROM_form.vhd and rename it to ROM_form.vhd.

You can run KCPSM3.EXE with wine and dosbox, it is terribly slow (dosbox). I still need to find a viable alternative.

wine KCPSM3.EXE fg_ctrl.psm

The output:

├── pico
│   ├── FG_CTRL.COE
│   ├── FG_CTRL.FMT
│   ├── FG_CTRL.LOG
│   ├── fg_ctrl.psm
│   ├── FG_CTRL.VHD
│   ├── KCPSM3.EXE
│   ├── LABELS.TXT
│   ├── no-jtag-Loader-ROM_form.vhd
│   ├── PASS1.DAT
│   ├── PASS2.DAT
│   ├── PASS3.DAT
│   ├── PASS4.DAT
│   ├── PASS5.DAT
│   ├── ROM_form.coe
│   └── ROM_form.vhd

Now you can copy FG_CTRL.VHD in the project folder.

Running an example design

s3esk_frequency_generator needs a special extra configuration in the bitstream generation process in order to tweak the DCM initialization. You can find further informations in the doc and in the vhdl source file.

I wasn’t able to add the configuration line as described in the doc, here is how I did.
In ISE right click “Generate Programming File” process and select “Design Goals & Strategies”. Here you can copy the default settings to a new strategy file (you need to save it and apply it to the project).

Add the following line to “Other Bitgen Command Line Options”:

-g cfg_dfs_s_x1y1:1111000011111111xxx111xxxxx1xxxxxxxxxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxxx01000000


TODO [DCM docs and oscilloscope outputs]


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