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IO pins
UCF file:
Clock and data input:
# # Period constraint for 50MHz operation # #NET "clk_50" PERIOD = 20.0ns HIGH 50%; # # soldered 50MHz Clock. # NET "clk_50_P" LOC = C9; NET "clk_50_P" IOSTANDARD = LVCMOS25; # 6 pin header J4 #NET "asi_rxdatan_P" LOC = "D7" | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; #NET "asi_rxdatap_P" LOC = "C7" | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; #NET "asi_txdatan_P" LOC = "F8" | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; #NET "asi_txdatap_P" LOC = "E8" | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; NET "asi_rxdatan_P" LOC = A6; NET "asi_rxdatan_P" IOSTANDARD = LVDS_25; NET "asi_rxdatan_P" DIFF_TERM = "TRUE"; NET "asi_rxdatap_P" LOC = B6; NET "asi_rxdatap_P" IOSTANDARD = LVDS_25; NET "asi_rxdatap_P" DIFF_TERM = "TRUE"; NET "asi_txdatan_P" LOC = E7; NET "asi_txdatan_P" IOSTANDARD = LVDS_25; NET "asi_txdatan_P" DIFF_TERM = "TRUE"; NET "asi_txdatap_P" LOC = F7; NET "asi_txdatap_P" IOSTANDARD = LVDS_25; NET "asi_txdatap_P" DIFF_TERM = "TRUE";
LEDs:
# # # Simple LEDs # Require only 3.5mA. # NET "asi_tx_active_P" LOC = F12; NET "asi_tx_active_P" IOSTANDARD = LVCMOS25; NET "asi_tx_active_P" DRIVE = 4; NET "asi_tx_active_P" SLEW = SLOW; NET "dcm_locked_P" LOC = E12; NET "dcm_locked_P" IOSTANDARD = LVCMOS25; NET "dcm_locked_P" DRIVE = 4; NET "dcm_locked_P" SLEW = SLOW; NET "framed_P" LOC = E11; NET "framed_P" IOSTANDARD = LVCMOS25; NET "framed_P" DRIVE = 4; NET "framed_P" SLEW = SLOW; #NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4; #NET "led<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4; NET "code_err_P" LOC = D11; NET "code_err_P" IOSTANDARD = LVCMOS25; NET "code_err_P" DRIVE = 4; NET "code_err_P" SLEW = SLOW; NET "disp_err_P" LOC = E9; NET "disp_err_P" IOSTANDARD = LVCMOS25; NET "disp_err_P" DRIVE = 4; NET "disp_err_P" SLEW = SLOW; NET "checker_err_P" LOC = F9; NET "checker_err_P" IOSTANDARD = LVCMOS25; NET "checker_err_P" DRIVE = 4; NET "checker_err_P" SLEW = SLOW;
Buttons:
# # # Press buttons # Must have pull DOWN resistors to provide Low when not pressed. # NET "pb0_rst_P" LOC = V4; NET "pb0_rst_P" IOSTANDARD = LVTTL; NET "pb0_rst_P" PULLDOWN; NET "pb2_clear_err_P" LOC = H13; NET "pb2_clear_err_P" IOSTANDARD = LVTTL; NET "pb2_clear_err_P" PULLDOWN; NET "pb3_reframe_P" LOC = K17; NET "pb3_reframe_P" IOSTANDARD = LVTTL; NET "pb3_reframe_P" PULLDOWN; NET "sync_mode_P" LOC = D18; NET "sync_mode_P" IOSTANDARD = LVTTL; NET "sync_mode_P" PULLDOWN; # # Rotary encoder. # Rotation contacts require pull UP resistors to provide High level. # Press contact requires pull DOWN resistor to provide Low when not pressed.. # #NET "rotary_a" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP; #NET "rotary_b" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP; NET "stimgen_en" LOC = V16; NET "stimgen_en" IOSTANDARD = LVTTL; NET "stimgen_en" PULLDOWN;
The buttons need to be inverted:
pb0_rst_S <= not pb0_rst_P; pb1_force_err_S <= not pb1_force_err_P; pb2_clear_err_S <= not pb2_clear_err_P; pb3_reframe_S <= not pb3_reframe_P; sync_mode_S <= not sync_mode_P; stimgen_en_S <= stimgen_en;
RPM placement:
# Net delay constraints NET "asi_datain" MAXDELAY = 0.7 ns; # RPM Constraints INST "asi_receiver/dru_8phase/QR" RLOC_ORIGIN = "X10Y90";
DRU
FPGA lines constraints (from FPGA editor):
attribute syn_keep of asi_datain : signal is TRUE; attribute route of asi_datain : signal is "{3;1;3s500efg320;8590666b!-1;-36072;80584;S!0;-159;0!1;-1724;"& "-1416!1;-49;-1263!1;1680;-1400!2;1748;-1240!2;-1708;-1240!2;1748;-1584!2;"& "-1708;-1584!3;73;-2081!3;73;-2425!4;1800;-1248!4;1800;-1592!5;327;0;L!6;"& "327;0;L!7;327;0;L!8;327;0;L!9;167;0;L!10;167;0;L!11;327;0;L!12;327;0;L!}";
Clockgen I
For the first version we use the same DCM configuration as the example application, just lowering down the input clock to 50MHz.