High speed serial link

Data communication

In order to achieve high speed communication you need to use a serial link. Beside costs parallel data becomes to difficult to handle due to clock skews.

Xilinx published an interesting book: High-Speed Serial I/O Made Simple. Even if you don’t plan to use and implement Gigabit channels, the techniques covered are essential and well presented.

Some standard are :

  • Gigabit Ethernet
  • JESD204b
  • Aurora

Thanks to encoding schemes it is possible to recover the clock from the data. If you stick with reasonably low speed data, oversampling is the easiest way to recover the data.

Oversampling

http://www.xilinx.com/support/documentation/application_notes/xapp1015.pdf

http://hamsterworks.co.nz/mediawiki/index.php/High_Speed_Link

Protocol layers

Level 0

nice intro to transmission lines
http://www.allaboutcircuits.com/textbook/alternating-current/chpt-14/50-ohm-cable/

http://www.digikey.com/product-search/en?mpart=AFBR-0548Z&vendor=516

Level 1 & 2

metastability (German)
http://www.lothar-miller.de/s9y/categories/35-Einsynchronisieren

Level 3, 4…

http://www.rtnet.org/doc.html

http://www.fpga4fun.com/10BASE-T.html

Line Encoding Schemes

Line encoding schemes modify raw data into a form that the receiver can accept. Specifically, the line encode scheme ensures that there are enough transitions for the clock recovery circuit to operate. They provide a means of aligning the data into words with a good direct current (DC) balance on the line.
Optionally, the line encoding scheme may also provide for implementation of clock correction, block synchronization and channel bonding, and division of the bandwidth into sub-channels.
There are two main line encoding schemes—value lookup schemes and self-modifying streams, or scramblers.

The 8-input bits are broken into 5- and 3-bit buses; that is how the names were developed. For example, the name Dx.y describes the data symbol for the input byte where the five least significant bits have a decimal value of x and the three most significant bits have a decimal value of y.

Xapp1015

asi-receiver-diagram

Import all vhd files.

Create FIFO from IP catalog:

  • Fifo generator
  • component name: dcfifo_2kx9
  • indipendent clocks, block RAM
  • write width: 9
  • write depth: 2048
  • read width: 9
  • write data count width (synchronized): 11
  • read data count width (synchronized): 11

Click generate, find the IP in Design Sources, right click and select generate output products

IO pins


Constrains

Clocks

All the clocks are generated from an external clock of 135MHz, using all the four DCMs available. Four clocks at 270MHz (135MHz 2X) 45° out of phase are used. The data is sampled at rising and falling edges, thus making an 8X oversampling.

  lk:for K in CLK270'range generate
       attribute loc of dc:label is "DCM_X"&INTEGER'image(K mod 2+1)&"Y"&INTEGER'image(K/2*3);
       attribute loc of bg:label is "BUFGMUX_X"&INTEGER'image(K mod 2+1)&"Y"&INTEGER'image(K/2*10);
     begin 
       dc:DCM_SP generic map(CLK_FEEDBACK=>"2X",
                             CLKDV_DIVIDE=>2.5,
                             CLKFX_DIVIDE=>1,
                             CLKFX_MULTIPLY=>4,
                             CLKIN_DIVIDE_BY_2=>FALSE,
                             CLKIN_PERIOD=>7.40741,
                             CLKOUT_PHASE_SHIFT=>"FIXED",
                             DESKEW_ADJUST=>"SYSTEM_SYNCHRONOUS",
                             DFS_FREQUENCY_MODE=>"LOW",
                             DLL_FREQUENCY_MODE=>"LOW",
                             DUTY_CYCLE_CORRECTION=>TRUE,
                             FACTORY_JF=>x"C080",
                             PHASE_SHIFT=>16*K,
                             STARTUP_WAIT=>FALSE)
                 port map(CLKFB=>iCLK270(K),
                          CLKIN=>CLK135_IN,
                          DSSEN=>'0',
                          PSCLK=>'0',
                          PSEN=>'0',
                          PSINCDEC=>'0',
                          RST=>RST,
                          CLKDV=>CLKDV(K),
                          CLKFX=>open,
                          CLKFX180=>open,
                          CLK0=>CLK0(K),
                          CLK2X=>CLK2X(K),
                          CLK2X180=>open,
                          CLK90=>open,
                          CLK180=>open,
                          CLK270=>open,
                          LOCKED=>LOCKED(K),
                          PSDONE=>open,
                          STATUS=>open);
       bg:BUFG port map(I=>CLK2X(K),O=>iCLK270(K));
     end generate;
  bd:BUFG port map(I=>CLKDV(0),O=>CLK54);
  b0:BUFG port map (I=>CLK0(0), O=>CLK135);
  CLK270<=iCLK270;

DRU

Data Recovery Unit

  signal asi_datain : std_logic;        -- Serial input data
  attribute syn_keep of asi_datain : signal is TRUE;
  attribute route of asi_datain : signal is "{3;1;3s1600efg400;691f401c!-1;94560;130400;S!0;-159;0!1;1680;"&
                                        "-1400!1;-49;-1263!1;-1724;-1416!2;1800;-1248!2;1800;-1592!3;73;-2081!3;"&
                                        "73;-2425!4;1748;-1240!4;-1708;-1240!4;1748;-1584!4;-1708;-1584!5;327;0;L!"&
                                        "6;327;0;L!7;167;0;L!8;167;0;L!9;327;0;L!10;327;0;L!11;327;0;L!12;327;0;L!}";

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